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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis / Edition 1
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis / Edition 1
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This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.